8D Corrective Action Report: LOT_WM811K_99

Current Status: SUCCESS (Attempt 1)

Executive Summary

An automated fab alert for Lot ID 'LOT_WM811K_99' triggered an end-to-end diagnostic pipeline. The Vision Worker identified a prominent 'Edge Ring' defect pattern affecting 187 dies with a spatial density score of 0.42. Subsequent root-cause analysis by the MoE RCA Worker traced the anomaly to ETCH_CHAMBER_04, identifying 'RF_Power_Variance_High' as the primary driver (93.7% confidence). Physical remediation requires replacing the worn focus ring, recalibrating the RF match network, and verifying ESC edge-zone temperature uniformity. To mitigate the silicon-level impact of this process variation, an adaptive Verilog compensation filter ('etch_polisher_compensation_filter') was generated. This module dynamically monitors process-monitor deviations, filters out high-frequency RF jitter, and adjusts the on-die bias/drive-strength DACs to maintain nominal performance across the wafer perimeter.

ASIC Compensation Patch

// ============================================================================
// etch_polisher_compensation_filter.v
// Lot: LOT_WM811K_99 | Tool: ETCH_CHAMBER_04 | Anomaly: RF_Power_Variance_High
// Function: On-die digital compensation of etch-induced process variation.
//           Filters process-monitor error and drives adaptive bias / drive-
//           strength correction codes to counteract RF power variance effects
//           (CD/drive-current spread) at the silicon level.
// ============================================================================
module etch_polisher_compensation_filter #(
    parameter MON_WIDTH      = 12,  // Process monitor code width
    parameter COMP_WIDTH     = 8,   // Compensation code width
    parameter FILTER_SHIFT   = 4,   // IIR filter coefficient (1/2^FILTER_SHIFT)
    parameter GAIN_NUM       = 3,   // Proportional gain numerator
    parameter GAIN_DEN_SHIFT = 2,   // Proportional gain denominator shift
    parameter SAT_EN         = 1    // Enable output saturation
)(
    input  wire                  clk,
    input  wire                  rst_n,
    input  wire                  mon_valid,
    input  wire [MON_WIDTH-1:0]  mon_code,   // Ring-oscillator process monitor
    input  wire [MON_WIDTH-1:0]  ref_code,   // Nominal (golden die) reference
    output reg  [COMP_WIDTH-1:0] comp_code,  // Signed compensation code to bias DAC
    output reg                   comp_valid,
    output wire                  alarm       // Variance beyond correctable range
);

    // 1. Error extraction: deviation induced by chamber RF power variance
    wire signed [MON_WIDTH:0] err_raw;
    assign err_raw = $signed({1'b0, mon_code}) - $signed({1'b0, ref_code});

    // 2. IIR low-pass filter: rejects high-frequency RF power jitter
    reg signed [MON_WIDTH+FILTER_SHIFT:0] filt_acc;
    always @(posedge clk or negedge rst_n) begin
        if (!rst_n)
            filt_acc <= {(MON_WIDTH+FILTER_SHIFT+1){1'b0}};
        else if (mon_valid)
            filt_acc <= filt_acc - (filt_acc >>> FILTER_SHIFT) + err_raw;
    end
    wire signed [MON_WIDTH:0] err_filt = filt_acc >>> FILTER_SHIFT;

    // 3. Proportional gain: scale filtered error into correction domain
    wire signed [MON_WIDTH+4:0] err_gain =
        (err_filt * GAIN_NUM) >>> GAIN_DEN_SHIFT;

    // 4. Saturating output stage: clamp to body-bias / drive-strength DAC range
    localparam signed [COMP_WIDTH-1:0] COMP_MAX = (1 << (COMP_WIDTH-1)) - 1;
    localparam signed [COMP_WIDTH-1:0] COMP_MIN = -(1 << (COMP_WIDTH-1));

    always @(posedge clk or negedge rst_n) begin
        if (!rst_n) begin
            comp_code  <= {COMP_WIDTH{1'b0}};
            comp_valid <= 1'b0;
        end else if (mon_valid) begin
            comp_valid <= 1'b1;
            if (SAT_EN && (err_gain > COMP_MAX))
                comp_code <= COMP_MAX;
            else if (SAT_EN && (err_gain < COMP_MIN))
                comp_code <= COMP_MIN;
            else
                comp_code <= err_gain[COMP_WIDTH-1:0];
        end else begin
            comp_valid <= 1'b0;
        end
    end

    // 5. Out-of-range alarm: escalate to eFuse trim or scan-dump disposition
    assign alarm = (err_gain > COMP_MAX) || (err_gain < COMP_MIN);

endmodule